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MPC2002 ? mpc2003 1 motorola fast sram 256kb and 512kb burstram ? secondary cache module for powerpc ? based systems the MPC2002sg and mpc2003sg are designed to provide a burstable, high performance, 256k/512k l2 cache for the powerpc 60x processors. the mod - ules are configured as 32k x 72 and 64k x 72 bits in a 136 pin dual readout single inline memory module (dimm). the module uses four of motorola' s mcm67m518 or mcm67m618 bicmos burstrams. bursts can be initiated with either transfer start processor (tsp ) or transfer start controller (tsc ). subsequent burst addresses are generated internal to the burstram by the burst address advance (baa ) pin. write cycles are internally self timed and are initiated by the rising edge of the clock (k) input. eight write enables are provided for byte write control. the cache family is designed to interface with the powerpc 60x bus and re- quires external tag. pd0 pd2 are reserved for density and speed identification. ? powerpcstyle burst counter on board ? dual readout simm for circuit density ? single 5 v 5% power supply ? all inputs and outputs are ttl compatible ? three state outputs ? byte parity ? byte write capability ? fast module clock rates: 66 mhz, 60 mhz, 50mhz ? decoupling capacitors for each fast static ram ? high quality multilayer fr4 pwb with separate power and ground planes ? i/os are 3.3 v compatible burstram is a trademark of motorola. powerpc and powerpc 601 are trademarks of international business machines corp. order this document by MPC2002/d semiconductor technical data MPC2002 mpc2003 (formerly mcm72ms32/64) 136lead dimm case 110401 top view 68 35 34 1 5/95 ? motorola, inc. 1995
pin assignment 136lead dimm case 110401 top view pd0 pd1 dq0 dq1 v cc dq4 dq6 dqp0 dq8 dq10 v ss k0 v ss dq14 v cc dq16 dq17 dq19 dq21 v cc dqp2 dq24 dq26 dq28 v ss dq31 dqp3 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 v ss pd2 v cc dq2 dq3 dq5 dq7 v ss dq9 dq11 dq12 v ss dq13 dq15 dqp1 v ss dq18 dq20 dq22 dq23 v ss dq25 dq27 dq29 dq30 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 w6 dq32 dq33 v ss dq36 dq38 dq39 dq40 v cc dq43 dq45 dq46 dqp5 v ss k1 v ss dq52 dq53 dq55 dqp6 v cc dq58 dq60 dq62 dqp7 a0 a2 a4 a6 a8 a10 a12 a14 v ss w7 e1 dq34 dq35 dq37 v cc dqp4 dq41 dq42 dq44 v ss dq47 dq48 dq49 v ss dq50 dq51 dq54 dq56 v ss dq57 dq59 dq61 dq63 v cc a1 a3 a5 a7 nc a9 a11 a13 a15* w0 w2 tsp baa e0 w1 w3 g0 tsc w4 g1 w5 v cc v ss v ss v ss pin names a0 a15 address inputs . . . . . . . . . . . . . . . . . . . . . . k0, k1 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . w0 w7 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . e0 , e1 module enable . . . . . . . . . . . . . . . . . . . . . . . . g0 , g1 module output enable . . . . . . . . . . . . . . . . . dq0 dq63 cache data input/output . . . . . . . . . . dqp0 dqp7 data parity input/output . . . . . . . . . tsc transfer start controller . . . . . . . . . . . . . . . . . . tsp transfer start processor . . . . . . . . . . . . . . . . . baa burst address advance . . . . . . . . . . . . . . . . . . pd0 pd2 presence detect . . . . . . . . . . . . . . . . . . v cc + 5 v power supply . . . . . . . . . . . . . . . . . . . . . . v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . * this pin on the MPC2002 is a no connect (nc) MPC2002 ? mpc2003 2 motorola fast sram pd2 pd1 pd0 cache size module v ss nc nc 512kb mpc2003sg66/60 v ss nc v ss 512kb mpc2003sg50 v ss v ss nc 256kb MPC2002sg66/60 v ss v ss v ss 256kb MPC2002sg50
MPC2002 ? mpc2003 3 motorola fast sram mpc2003 (64k x 72) module block diagram lw mcm67m618 a0 a15 baa k g e dq0 dq7 a0 a15 e0 16 k1 e1 g1 dq8 uw tsp tsc dq9 dq16 dq17 baa tsp tsc k0 g0 dq0 dq7 dqp0 dq8 dq15 dqp1 w0 w1 8 8 lw mcm67m618 a0 a15 baa k g e dq0 dq7 dq8 uw tsp tsc dq9 dq16 dq17 dq16 dq23 dqp2 dq24 dq31 dqp3 w2 w3 8 8 lw mcm67m618 a0 a15 baa k g e dq0 dq7 dq8 uw tsp tsc dq9 dq16 dq17 dq32 dq39 dqp4 dq40 dq47 dqp5 w4 w5 8 8 lw mcm67m618 a0 a15 baa k g e dq0 dq7 dq8 uw tsp tsc dq9 dq16 dq17 dq48 dq55 dqp6 dq56 dq63 dqp7 w6 w7 8 8
MPC2002 ? mpc2003 4 motorola fast sram MPC2002 (32k x 72) module block diagram lw mcm67m518 a0 a14 baa k g e dq0 dq7 a0 a14 e0 15 k1 e1 g1 dq8 uw tsp tsc dq9 dq16 dq17 baa tsp tsc k0 g0 dq0 dq7 dqp0 dq8 dq15 dqp1 w0 w1 8 8 lw mcm67m518 a0 a14 baa k g e dq0 dq7 dq8 uw tsp tsc dq9 dq16 dq17 dq16 dq23 dqp2 dq24 dq31 dqp3 w2 w3 8 8 lw mcm67m518 a0 a14 baa k g e dq0 dq7 dq8 uw tsp tsc dq9 dq16 dq17 dq32 dq39 dqp4 dq40 dq47 dqp5 w4 w5 8 8 lw mcm67m518 a0 a14 baa k g e dq0 dq7 dq8 uw tsp tsc dq9 dq16 dq17 dq48 dq55 dqp6 dq56 dq63 dqp7 w6 w7 8 8 a15 nc
MPC2002 ? mpc2003 5 motorola fast sram block diagram (see note) external address 16 9 9 18 16 a15 a2 dq0 dq8 internal address 64k x 18 memory array address registers write register enable register datain registers output buffer baa k tsp tsc a15 a0 uw e g 9 dq9 dq17 9 9 9 lw a0 a1 a1 load d1 binary counter d0 q1 q0 burst logic a0 note: all registers are positiveedge triggered. the tsc or tsp signals control the duration of the burst and the start of the next burst. when tsp is sampled low , any ongoing burst is interrupted and a read (independent of w and tsc ) is performed using the new external address. alternatively, a tsp initiated two cycle write can be performed by asserting tsp and a valid address on the first cycle, then negating both tsp and tsc and asserting l w and/or uw with valid data on the se - cond cycle (see single write cycle in write cycles timing diagram). when tsc is sampled low (and tsp is sampled high), any ongoing burst is interrupted and a read or write (dependent on w ) is performed using the new external address. chip enable (e ) is sampled only when a new base address is loaded. after the first cycle of the burst, baa controls subsequent burst cycles. when baa is sampled low, the internal address is ad- vanced prior to the operation. when baa is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. upon completion of a burst, the address will wrap around to its initial state. see burst sequence graph . write refers to either or both byte write enables (lw , uw ). burst sequence graph (see note) 1,0 1,1 0,0 0,1 a1 , a0 = note: the external two values for a1 and a0 provide t h e s tartin g p oin t f o r t h e b urst sequence g raph . t h e b urs t l ogi c a d- vances a1 and a0 as shown above.
MPC2002 ? mpc2003 6 motorola fast sram synchronous truth table (see notes 1, 2, and 3) e tsp tsc baa lw or uw k address operation h l x x x lh n/a deselected h x l x x lh n/a deselected l l x x x lh external address read cycle, begin burst l h l x l lh external address write cycle, begin burst l h l x h lh external address read cycle, begin burst x h h l l lh next address write cycle, continue burst x h h l h lh next address read cycle, continue burst x h h h l lh current address write cycle, suspend burst x h h h h lh current address read cycle, suspend burst notes: 1. x means don't care. 2. all inputs except g must meet setup and hold times for the lowtohigh transition of clock (k). 3. w ait states are inserted by suspending burst. asynchronous truth table (see notes 1 and 2) operation g i/o status read l data out (dq0 dq8) write x highz e data in deselected x highz notes: 1. x means don't care. 2. for a write operation following a read operation, g must be high before the input data required setup time and held high through the input data hold time. absolute maximum ratings (voltages referenced to v ss = 0 v) rating symbol value unit power supply voltage v cc 0.5 to + 7.0 v voltage relative to v ss for any pin except v cc v in , v out 0.5 to v cc + 0.5 v output current (per i/o) i out 30 ma power dissipation p d 6.0 w temperature under bias t bias 10 to + 85 c operating temperature t a 0 to +70 c storage temperature t stg 55 to + 125 c note: permanent device damage may occur if absolute maximum ra tings are exceeded. functional operation should be restricted to recommended oper - ating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. this device contains circuitry to protect the inputs against damage due to high static volt - ages or electric fields; however , it is advised that normal precautions be taken to avoid application of any voltage higher than maxi - mum rated voltages to this highimpedance circuit. this bicmos memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. this device contains circuitry that will ensure the output devices are in highz at power up.
MPC2002 ? mpc2003 7 motorola fast sram dc operating conditions and characteristics (v cc = 5.0 v 5%, t a = 0 to + 70 c, unless otherwise noted) recommended operating conditions (voltages referenced to v ss = 0 v) parameter symbol min max unit supply voltage (operating voltage range) v cc 4.75 5.25 v input high voltage v ih 2.2 v cc + 0.3 ** v input low voltage v il 0.5* 0.8 v * v il (min) = 0.5 v dc; v il (min) = 2.0 v ac (pulse width 20.0 ns) for i 20.0 ma. ** v ih (max) = v cc + 0.3 v dc; v ih (max) = v cc + 2.0 v ac (pulse width 20.0 ns) for i 20.0 ma. dc characteristics and supply currents parameter symbol min max unit input leakage current (all inputs, v in = 0 to v cc ) i lkg(i) e 1.0 m a output leakage current (g = v ih ) i lkg(o) e 1.0 m a ac supply current (g = v ih , e = v il , i out = 0 ma, all inputs = v il or v ih , v il = 0.0 v and v ih 3.0 v, cycle time t khkh min) i cca66 i cca60 i cca50 e 1160 1100 1000 ma ac standby current (e = v ih , i out = 0 ma, all inputs = v il and v ih, v il = 0.0 v and v ih 3.0 v, cycle time t khkh min) i sb1 e 300 ma output low voltage (i ol = + 8.0 ma) v ol e 0.4 v output high voltage (i oh = 4.0 ma) v oh 2.4 3.3 v note: good decoupling of the local power supply should always be used. dc characteristics are guaranteed for all possible powerpc bus cycles. capacitance (f = 1.0 mhz, dv = 3.0 v, t a = 25 c, periodically sampled rather than 100% t ested) parameter symbol typ max unit input capacitance (a0 a15, tsp , tsc , baa ) c in 25 32 pf input/output capacitance (dq0 dq63, dqp0 dqp7) c i/o 8 10 pf input capacitance (kx, gx , ex , wx ) c in 12 15 pf
MPC2002 ? mpc2003 8 motorola fast sram ac operating conditions and characteristics (v cc = 5.0 v 5% t a = 0 to + 70 c, unless otherwise noted) input t iming measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 3 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output timing reference level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . output load see figure 1a unless otherwise noted . . . . . . . . . . . . read/write cycle timing (see notes 1, 2, and 3) (w refers to either or both byte write enables) MPC2002sg66/ mpc2003sg66 MPC2002sg60/ mpc2003sg60 MPC2002sg50/ mpc2003sg50 parameter symbol min max min max min max unit notes cycle time t khkh 15 e 16.6 e 20 e ns clock access time t khqv e 9 e 11 e 14 ns 4 output enable to output valid t glqv e 5 e 5 e 6 ns clock high to output active t khqx1 6 e 6 e 6 e ns clock high to output change t khqx2 3 e 3 e 3 e ns output enable to output active t glqx 0 e 0 e 0 e ns output disable to q highz t ghqz 2 6 2 6 2 6 ns 5 clock high to q highz t khqz e 6 e 6 e 6 ns 5 clock high pulse width t khkl 5 e 5 e 6 e ns clock low pulse width t klkh 5 e 5 e 6 e ns setup times: address address status data in write address advance chip select t avkh t tsvkh t dvkh t wvkh t bavkh t evkh 2.5 e 2.5 e 2.5 e ns 6 hold times: address address status data in write address advance chip select t khax t khtsx t khdx t khwx t khbax t khex 0.5 e 0.5 e 0.5 e ns 6 notes: 1. a read cycle is defined by uw and l w high or tsp low for the setup and hold times. a write cycle is defined by l w or uw low and tsp high for the setup and hold times. 2. all read and write cycle timings are referenced from k or g . 3. g is a don't care when uw or lw is sampled low. 4. maximum access times are guaranteed for all possible powerpc 60x external bus cycles. 5. transition is measured 500 mv from steadystate voltage with load of figure 1b. this parameter is sampled and not 100% tested. at any given voltage and temperature, t khqz max is less than t khqx1 min for a given device and from device to device. 6. this is a synchronous device. all addresses must meet the specified setup and hold times for all rising edges of clock (k) whenever tsp or tsc are low and the chip is selected. all other synchronous inputs must meet the specified setup and hold times for all rising edges of k when the chip is selected.chip enable must be valid at each rising edge of clock for the device (when tsp or tsc is low) to remain enabled. ac test loads figure 1a figure 1b 5 pf + 5 v output 480 w 255 w output z 0 = 50 w r l = 50 w v l = 1.5 v
MPC2002 ? mpc2003 9 motorola fast sram q(a2 + 2) q(a2 + 1) q(a2) q(a2 + 3) q(a2 + 2) q(a2 + 1) q(a2) q(a1) burst read (baa suspends burst) (burst wraps around to its initial st ate) single read tsc t khqz t khqv t khqx2 t ghqz t glqx t glqv t khqv t khbax t bavkh t khex t evkh t khwx t wvkh t khtsx t tsvkh t khax t avkh t klkh t khkl t tsvkh t khkh t khtsx data out g e k tsp address lw, uw note: q(a2) represents the first output data from the base address a2; q(a2 + 1) represents the next output data in the burst sequence with a2 as the base address. a1 a2 baa read cycles
MPC2002 ? mpc2003 10 motorola fast sram w is ignored for first cycle when tsp initia tes burst new burst write burst write baa suspends burst t khdx t dvkh t khbax t bavkh t khwx t wvkh tsc st arts new burst a3 t khsx t tsvkh t khkh t khkl t klkh t khtsx t tsvkh t khax t avkh t khex t evkh single write burst read t ghqz k tsp tsc a baa g d q write cycles a1 a2 e lw, uw q(an 1) q(an) d(a3 + 2) d(a3 + 1) d(a3) d(a2 + 3) d(a2 + 2) d(a2 + 1) d(a2) d(a2 + 1) d(a1) (with a suspended cycle)
MPC2002 ? mpc2003 11 motorola fast sram combination read/write cycle (e low, tsc high) k tsp address lw , uw baa g data in data out read write burst read t khkh t tsvkh t khtsx t khkl t klkh a1 a2 a3 t avkh t khax t wvkh t khwx t bavkh t khbax t khqv t khqx1 t ghqz t dvkh t khdx t glqx t khqx2 d(a2) q(a1) q(a3) q(a3 + 1) q(a3 + 2) t glqv
MPC2002 ? mpc2003 12 motorola fast sram application example 512k byte burstable, secondary cache using mpc2003sg66 with a 66 mhz mpc601 powerpc ? data address (powerpc ? ) bclk ts control cache control logic baa tsp k0 tsc wx g0 data bus address bus mcm67m618fn9 mpc601 clock addr addr data k figure 2 mpc2003sg66 k1 g1 ordering information (order by full part number) motorola memory prefix part number package (sg = gold pad simm) speed (66 = 66 mhz, 60 = 60 mhz, 50 = 50 mhz) mcm MPC2002 mpc2003 xx xx full part numbers e MPC2002sg66 MPC2002sg60 MPC2002sg50 mpc2003sg66 mpc2003sg60 mpc2003sg50
MPC2002 ? mpc2003 13 motorola fast sram package dimensions 136lead dimm case 110401 x 0.006 (0.15) t y l 0.012 (0.30) m component area view aa front view 136x k 2x q dim a min max min max millimeters 4.045 4.055 102.74 103.00 inches b 0.995 1.005 25.27 25.53 c 0.413 10.50 d 0.040 0.042 1.02 1.07 f 0.125 bsc 0.064 3.18 bsc g 0.010 0.25 h j 0.046 0.054 1.17 1.37 k 0.100 2.54 l m 1.650 bsc 41.91 bsc n 0.400 bsc 10.16 bsc p 0.125 3.18 q 0.123 0.127 3.12 3.22 r 0.245 0.255 6.22 6.48 s notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. card thickness applies across tabs and includes plating and/or metallization. 4. dimensions c and s define a doublesided module. 5. dimension v defines optional singlesided module. 6. straightness callout applies to tab area only. t 3.784 bsc w 0.050 bsc 1.27 bsc u v y 0.060 0.064 1.52 1.63 0.075 0.085 1.91 2.16 0.060 1.52 1.63 0.157 4.00 0.236 6.00 1.57 0.062 96.11 bsc ??????? ??????? ??????? ??????? ?????? ?????? ?????? ?????? component area back view ?? ?? ?? ?? ? ? ? ? ?? ?? ?? ?? ? ? ? ? u f x 0.006 (0.15) t y s a m 2x n 2x 2x l r y b -y- -x- view aa 1 34 35 68 69 102 103 136 side view -t- 2x w 2x w r m 136x h 136x d m x 0.004 (0.10) t y s l g 132x c note 4 s note 4 v note 5 p j r t note 6 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters can and do vary in dif ferent applications. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af firmative action employer .
MPC2002 ? mpc2003 14 motorola fast sram literature distribution centers: usa/europe: motorola literature distribution; p .o. box 20912; phoenix, arizona 85036. jap an: nippon motorola ltd.; 4321, nishigotanda, shinagawaku, t okyo 141, japan. asia p acific: motorola semiconductors h.k. ltd.; silicon harbour center , no. 2 dai king street, t ai po industrial estate, t ai po, n.t., hong kong. MPC2002/d ?

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